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       ADSP-21161 EZ-Kit Link Port Boot Master Routine

Sets up a core driven link port transfer through Link Port 0 to a slave ADSP-21161 

Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062

August-2003 Andrew Caldwell

This directory contains an example ADSP-21161 subroutine that implements a Link Port
boot of a slave ADSP-21161.  


Files contained in this directory and it's sub-directories:

ADSP-21161_ASM.ldf				Linker description file 
Master.dpj						VisualDSP++ 3.0 project file
Master.mak						VisualDSP++ 3.0 Make file
Master.asm						Source file for master ADSP-21161
Interrupt_vectors.asm			Source file for master ADSP-21161
defines.h						Master header file
Interrupt_vectors.doj			VisualDSP++ 3.0 object file
Master.doj						VisualDSP++ 3.0 object file
Master.dxe						VisualDSP++ 3.0 executable file
README_Master.txt				This README file
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CONTENTS

I.    MASTER SOURCE DESCRIPTION
II.   KERNEL FILE DESCRIPTION
III.  LOADER FILE DESCRIPTION
         

I. MASTER SOURCE DESCRIPTION

Description:																		
This program requires two ADSP-21161 EZ-KIT Lite development boards and a link port 
cable to attach the two boards. One EZ-KIT must be configured for link boot.
The program may also be used in a master DSP in an ADSP-21161 MP cluster in which a 
slave ADSP-21161 is configured for link port boot.																
																					
The file to be booted is a simple blink example that flashes LED 2,3,4,5,6,and 7	
on the ADSP-21161N EZ-KIT Lite Evaluation Platform. These LEDs are connected to 	
flags 9, 8, 7, 6, 5 and 4 respectively. If running on a different platform then
the source should be altered according to the specific hardware.												
																					
The defined value "size" located in "defines.h" refers to the number of 16 bit words 
contained in the loader file that is to boot the slave DSP. This value should be altered
to match the number of 16 bit words contained in the loader file that you wish to transmit.
The loader file to be transmitted is stored as an array named "_ldr_source" declared in 
"Master.asm". The name of the loader file and the size are all the alerations that are 
required when using two ADSP-21161 EZ-KIT Lite development boards.
																					
The loader file is stored in 32-bit memory with each 16-bit word located in the lower 16-bits
of each 32-bit memory location.

The 16 bit words from the "_ldr_source" buffer must be packed into a 48-bit instruction
before being written to the link port transmit buffer. The loader file is of the format that 
the first 16-bit word is the least significant 16 bit words of the 48-bit instruction, the next 
16-bit word is the middle 16-bits of the 48-bit instruction and the third 16-bit word is the 16
most significant bits of the 48-bit instruction. This is the same for ASCII or Include
loader file formats.																	  

There are 3 main routines in the Master.asm source file:
"__tx_kernel"
"__tx_code"
"__tx_instructions"

Both "tx_kernel" and "__tx_code" call the "__tx_instructions" routine. The only difference being 
that the "__tx_kernel" routine passes a count value of 256 to the "__tx_instructions" routine.
The "__tx_code" routine passes the remaining number of 48 bit words to the "__tx_instructions"
routine. There is no necessity to have the functions split up in this manner, the entire loader file
could be transmitted from one routine however for it allows for easier indication that at least the
256 word kernel has been transmitted successfully before moving on to the rest of the application code.

The "__tx_instructions" routine is set up to run either "kernel_count" or "count" times to transmit  
either the first 256 words or the remainder of the application code and data.									 	
The loop consists of three parts. The first is "__test_lbuf". This reads the value of the link  	
port common control register to check if the link port buffer is full, if the buffer is full	
then it continually monitors this register until the buffer is not full. If the buffer is  	
not full then three 16-bit words are read and packed into the px register using px1 and px2 	
to create the 48-bit instruction to be transmitted. This instruction is then written to the link port
buffer 0.

	
II.   KERNEL FILE DESCRIPTION

Description:
The kernel files used to build the loader files are found in the "161_Link/Debug" folder of "EE199.zip".
4 kernel files have been created:

"161_Link.dxe"
"161_Link_Debug.dxe"
"161_Link_SDRAM.dxe"
"161_Link_SDRAM_Debug.dxe"

"161_Link.dxe" has no SDRAM configuration included and was built without "PAUSE" defined. This kernel is
suitable for creating loader files for systems that have no external SDRAM and no link port booting 
debugging is required.

"161_Link_Debug.dxe" has no SDRAM configuration included and was built with "PAUSE" defined. This kernel is
suitable for creating loader files for systems that have no external SDRAM in which the user would like to
monitor or debug the link port booting process.


"161_Link_SDRAM.dxe" has SDRAM configuration included (default set for ADSP-21161 EZ-KIT Lite SDRAM) and was 
built without "PAUSE" defined. This kernel is suitable for creating loader files for systems that have 
external SDRAM and no link port booting debugging is required.

"161_Link_SDRAM_Debug.dxe" has SDRAM configuration included (default set for ADSP-21161 EZ-KIT Lite SDRAM) 
and was built with "PAUSE" defined. This kernel is suitable for creating loader files for systems that have 
external SDRAM in which the user would like to monitor or debug the link port booting process.

For details on the effects of defining "PAUSE" when building the kernel see the kernel source code "161_Link.asm"
and "EE-199 Link Port Booting the ADSP-21161"


III.  LOADER FILE DESCRIPTION
Description:
4 loader files are included in "EE-199.zip" and are located in "../Link Loader Files"
These four loader files are:

"Blink_Example.ldr"
"Blink_Example_Debug.ldr"
"Blink_Example_SDRAM.ldr"
"Blink_Example_SDRAM_Debug.ldr"

Each of the loader files has been created with one of the four kernels as described in II

